Senior SI/PI Engineer for AI Hardware & 3D Packaging

Google

Sunnyvale (CA)

On-site

USD 163,000 - 236,000

Full time

4 days ago

Be an early applicant

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Google LLC in Sunnyvale, CA, is seeking a Senior Signal and Power Integrity Engineer to lead SI/PI design and verification for high-performance systems, including AI/ML hardware accelerators. You will collaborate across chip design, IP, and system teams to ensure robust SI/PI performance from concept to production.

Ideal candidates bring advanced lab bring-up, scripting in Python/Matlab/C++, and strong experience with 2.5D/3D packaging and memory interfaces.

Qualifications

8 years of SI/PI design experience in chip/package or system PCB.
Experience with lab bring-up and characterization for high-speed memory and SerDes.
Experience with partnering across chip architecture, physical design, STA, package, and validation teams.

Responsibilities

Lead chip and package SI/PI analysis and optimization for HPC leveraging advanced 2.5D/3D packaging technologies.
Partner early in product definition to influence chip floor planning, PDN/power trees, netlists, and routability tradeoffs.
Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries.
Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure.
Partner with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency.