ASIC Packaging SI/PI Engineer [Hybrid]

AnySilicon; San Jose (CA); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Cisco Silicon One in San Jose, CA is seeking a Signal and Power Integrity Engineer to join its specialized ASIC team. You will develop and verify next-generation ASIC packaging, ensuring high performance and reliability in complex silicon designs.

Responsibilities include creating design rules for ultra-high-speed signaling, analyzing SI/PI across interposer, substrate, and PCB, and collaborating with system partners to resolve tough technical issues.

Formación

• Bachelors with 2 years of related experience or Masters with 0 years.
• Experience with high-speed design principles and SI/PI analysis using industry tools.
• Experience with pre- and post-layout SI/PI analysis and lab measurements.

Responsabilidades

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate SI and PI, collaborating with layout to optimize interposer, substrate, and PCB solutions.
• Design and develop ASIC packages for high-volume releases, including post-layout extraction and reporting.
• Collaborate with partners and design leads to resolve complex technical issues.

Conocimientos

High-speed design principles

Transmission Line Theory

Impedance network analysis

SI/PI characterization

Measurement planning

Educación

Bachelor's degree in related field

Master's degree in related field

Herramientas

Cadence Sigrity

Ansys HFSS

Descripción del empleo

Cisco Silicon One is seeking a Signal and Power Integrity Engineer to join their specialized ASIC team in San Jose, CA. This role involves developing and verifying next-generation ASIC packaging for various Cisco platforms, ensuring high-performance and reliability in complex silicon designs.

Responsibilities:

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate signal integrity (SI) and power integrity (PI), collaborating with the layout team to optimize solutions across interposer, substrate, and PCB.
• Design and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and resolve complex technical issues.

Qualifications:

• Bachelor's degree with 2 years of related experience, or Master's degree with 0 years of related experience.
• Experience with high-speed design principles, including Transmission Line Theory and impedance network analysis, specifically for 56G PAM4 SerDes architectures.
• Experience in pre- and post-layout signal and power integrity analysis using industry-standard EDA tools and lab measurements.

Skills:

• Proficiency in SI/PI simulation and validation using tools like Cadence Sigrity and Ansys HFSS.
• Experience with measurement planning and execution, including VNA measurements and full channel characterization.
• Ability to perform SI/PI characterization and debug high-speed systems using advanced equipment.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Work Email

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