Senior Silicon Design Verification Engineer (DFT/ATPG)

Socket.dev; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

AMD in San Jose, CA is hiring a SMTS Silicon Design Engineer to work in front-end design/integration, collaborating with architecture, IP design, and Physical Design teams to achieve first pass silicon success. The role emphasizes DFT implementation, scan insertion, ATPG generation, and post-silicon support for yield learning.

The candidate should have strong accuracy, communication, and problem-solving skills, plus experience with DFT methodologies and related EDA tools.

Qualifications

• Design for Test methodologies and DFT verification experience (IEEE1500, JTAG 1149.x, Scan, memory BIST).
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX.
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

Skills

DFT verification

Scan insertion

ATPG

Gate-level simulation

Verilog RTL design

IEEE1500

JTAG 1149.x

memory BIST

Perl/Shell scripting

Education

Bachelor's or master's degree in computer engineering/Electrical Engineering

Tools

Mentor testkompress

Synopsys Tetramax/DFTMAX

VCS

Job description

AMD in San Jose, CA is hiring a SMTS Silicon Design Engineer to work in front-end design/integration, collaborating with architecture, IP design, and Physical Design teams to achieve first pass silicon success. The role emphasizes DFT implementation, scan insertion, ATPG generation, and post-silicon support for yield learning.

The candidate should have strong accuracy, communication, and problem-solving skills, plus experience with DFT methodologies and related EDA tools.