DFT Architect — SoC/FPGA Test & Yield Optimizer

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD in San Jose, California is seeking a DFT Architect to drive DFT architecture across Scan, MBIST, PHY, and high-speed IOs for next-generation products. This role interacts with design architecture, DFT/DFX, and physical design teams to enable manufacturable solutions and early silicon success.

We expect strong DFT expertise, leadership, and the ability to communicate complex engineering topics to cross-functional teams and upper management. This position is site-based in San Jose.

Qualifications

• MS or PhD in Electrical/Electronic/Computer Engineering.
• Strong DFT engineering experience with manufacturing test emphasis.
• Experience with Scan, MBIST, PHY, and high-speed IOs in SoC contexts.

Responsibilities

• Promote ATE and production test environment improvements in future AMD products.
• Manage DFT activities across architecture, design, verification and test implementation.
• Coordinate with design teams to ensure DFT structures are correctly implemented.
• Drive internal DFT teams to implement robust test solutions.
• Plan diagnosability and yield improvement initiatives.

Skills

DFT architecture

Leadership

Communication

Verilog/HDL knowledge

Cross-functional collaboration

Education

MS or Ph.D. in Electrical/Electronic/Computer Engineering

Tools

Tessent SSN

ATPG tools

Job description

AMD in San Jose, California is seeking a DFT Architect to drive DFT architecture across Scan, MBIST, PHY, and high-speed IOs for next-generation products. This role interacts with design architecture, DFT/DFX, and physical design teams to enable manufacturable solutions and early silicon success.

We expect strong DFT expertise, leadership, and the ability to communicate complex engineering topics to cross-functional teams and upper management. This position is site-based in San Jose.