Senior Silicon Development Engineer — DFT & Bring-Up

Socket.dev; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose, CA is seeking a DFT engineer to implement and verify DFT architectures and features. You will perform scan insertion, ATPG pattern generation, and gate-level ATPG verification, contributing to post-silicon yield learning.

The candidate should have hands-on experience with DFT methodologies, Mentor Testkompress or Synopsys Tetramax/DFTMAX, and Verilog RTL design, with strong problem-solving and communication skills.

Qualifications

• Understanding of Design for Test methodologies and DFT verification experience (IEEE1500, JTAG 1149.x, Scan, memory BIST).
• Experience with Mentor Testkompress and/or Synopsys Tetramax/DFTMAX.
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis; post-silicon support to ensure successful bring up and yield learning

Skills

IEEE1500 / JTAG / Scan / memory BIST

Education

Bachelor's or master's in Computer/Electrical Engineering

Tools

Mentor Testkompress

Synopsys Tetramax/DFTMAX

VCS

Perl/Shell scripting

Verilog RTL design

Job description

AMD in San Jose, CA is seeking a DFT engineer to implement and verify DFT architectures and features. You will perform scan insertion, ATPG pattern generation, and gate-level ATPG verification, contributing to post-silicon yield learning.

The candidate should have hands-on experience with DFT methodologies, Mentor Testkompress or Synopsys Tetramax/DFTMAX, and Verilog RTL design, with strong problem-solving and communication skills.