Senior CPU Core DFT Engineer

Advanced Micro Devices; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

AMD in Santa Clara, CA seeks a senior DFT engineer to own ATPG/DFT responsibilities for the next generation of high-performance cores. You will collaborate with architecture, IP design, Physical Design, and Product engineering to achieve first pass silicon success.

Ideal candidates have hands-on DFT/ATPG, MBIST/LBIST knowledge, Verilog proficiency, debugging skills, Linux comfort, and scripting with Perl/TCL. This role directly impacts silicon quality and delivery timelines.

Qualifications

• Experience with DFT tools, ATPG and scan compression.
• Debug low coverage and fix DRC/issue resolution.
• Proficient in logic design using Verilog.
• Debugging complex test pattern issues and simulations.
• Support silicon bring-up and post-silicon debug.
• Comfortable in Linux and scripting (Perl, TCL).
• Knowledge of DFT standards (ATPG, JTAG, MBIST; IEEE 1149.x, 1500, 1687).
• Strong presentation and communication skills.
• Bachelor's in Electrical Engineering/Computer Engineering.

Responsibilities

• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Debug of low coverage, DRC violation fixes and efficient solutions.
• Proficient in logic design using Verilog.
• Debugging complex test pattern issues and simulation failures.
• Support of Silicon bring up activities.
• Participating in post-silicon debug.
• Comfortable in Linux environment and scripting languages (Perl, TCL).
• Knowledge about DFT standards and trade-offs in test quality vs. time.
• Strong communication and collaboration with cross-functional teams.
• Bachelor's in Electrical Engineering/Computer Engineering.

Skills

DFT

ATPG

Scan compression

Verilog

Linux

Debugging test patterns

Communication skills

Scripting

Education

Bachelor's in Electrical Engineering or Computer Engineering

Tools

Perl

TCL

Job description

AMD in Santa Clara, CA seeks a senior DFT engineer to own ATPG/DFT responsibilities for the next generation of high-performance cores. You will collaborate with architecture, IP design, Physical Design, and Product engineering to achieve first pass silicon success.

Ideal candidates have hands-on DFT/ATPG, MBIST/LBIST knowledge, Verilog proficiency, debugging skills, Linux comfort, and scripting with Perl/TCL. This role directly impacts silicon quality and delivery timelines.