Senior CPU Core DFT Engineer - ATPG/DFT Lead

AMD; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

AMD in Santa Clara, CA, is seeking a senior DFT Engineer to own ATPG/DFT for the next generation of high‑performance cores. You will work closely with architecture, IP design, Physical Design, and Product Engineering to ensure first‑pass silicon success.

The role requires hands‑on experience with DFT tools and test patterns, with strong Verilog and Linux scripting skills. Candidates should be comfortable collaborating across teams and participating in post‑silicon debug.

Qualifications

• Bachelor’s or Master’s in Electrical/Computer Engineering.
• Experience with DFT, ATPG, and scan compression.
• Familiar with Linux and scripting (Perl, TCL).

Responsibilities

• Own ATPG/DFT for AMD high‑performance cores.
• Collaborate with architecture, IP design, physics, and product engineering teams.
• Debug low coverage, DRC fixes and optimize test quality vs. time.
• Support silicon bring‑up activities and post‑silicon debug.
• Work in Linux environment and use scripting languages.

Skills

DFT concepts

ATPG

Verilog

Linux scripting

Problem solving

Education

BSc/MSc in EE/CE

Tools

Tessent

MBIST

Job description

AMD in Santa Clara, CA, is seeking a senior DFT Engineer to own ATPG/DFT for the next generation of high‑performance cores. You will work closely with architecture, IP design, Physical Design, and Product Engineering to ensure first‑pass silicon success.

The role requires hands‑on experience with DFT tools and test patterns, with strong Verilog and Linux scripting skills. Candidates should be comfortable collaborating across teams and participating in post‑silicon debug.