Senior Silicon Development Engineer — DFT & Validation Lead

Advanced Micro Devices; San Jose (CA); Hybrid; USD 110,000 - 150,000; Full time

Job summary

AMD in San Jose, CA, is seeking a front-end design/integration engineer within the Radeon Technologies Group to help bring to life cutting-edge silicon designs. You will work with architecture, IP design, Physical Design, and product engineers to achieve first pass silicon success.

The role requires meticulous, detail-oriented candidates with strong communication, problem-solving skills and experience with DFT methodologies, scan insertion, ATPG, and verification, contributing to successful

Qualifications

• Bachelor's or master's degree in computer engineering or electrical engineering.
• Experience with Design for Test methodologies and DFT verification.
• Ability to work with cross-functional teams and meet bring-up milestones.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

Skills

DFT verification

Scan insertion

ATPG pattern generation

Verilog RTL design

VCS simulation

Perl/Shell scripting

Problem solving

Education

Bachelor's or master's degree in Computer Engineering / Electrical Engineering

Tools

Mentor TestKompress

Synopsys Tetramax/DFTMAX

VCS

Job description

AMD in San Jose, CA, is seeking a front-end design/integration engineer within the Radeon Technologies Group to help bring to life cutting-edge silicon designs. You will work with architecture, IP design, Physical Design, and product engineers to achieve first pass silicon success.

The role requires meticulous, detail-oriented candidates with strong communication, problem-solving skills and experience with DFT methodologies, scan insertion, ATPG, and verification, contributing to successful