Senior DFT & Silicon Verification Engineer

Advanced Micro Devices; San Jose (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Advanced Micro Devices in San Jose, CA is seeking an SMTS Silicon Design Engineer to join the Radeon Technologies Group. You will contribute to front-end design/integration, coordinating with architecture, IP design, and physical design teams to achieve first pass silicon success and strong yield learning.

The role emphasizes rigorous DFT implementation/verification, test pattern generation, and post-silicon support, requiring keen attention to detail and clear communication with senior

Qualifications

• Understanding of Design for Test methodologies and DFT verification experience (e.g. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
• Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• ATPG patterns verification with gate-level simulation
• Test coverage and test cost reduction analysis
• Post silicon support to ensure successful bring up and enhance yield learning

Skills

DFT verification

IEEE1500/JTAG

Scan

ATPG

VCS

Verilog RTL

Perl/Shell scripting

Memory BIST

Education

Bachelor's or master's degree in computer engineering/Electrical Engineering

Tools

Mentor testkompress

Synopsys Tetramax/DFTMAX

VCS

Job description

Advanced Micro Devices in San Jose, CA is seeking an SMTS Silicon Design Engineer to join the Radeon Technologies Group. You will contribute to front-end design/integration, coordinating with architecture, IP design, and physical design teams to achieve first pass silicon success and strong yield learning.

The role emphasizes rigorous DFT implementation/verification, test pattern generation, and post-silicon support, requiring keen attention to detail and clear communication with senior