Senior Staff Silicon DFT Architect (SoCs)

AMD; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD in San Jose seeks a Senior Staff Silicon Design Engineer to lead DFT strategy and bring-up across SoCs, collaborating with architecture, verification, physical design and manufacturing teams.

You will drive test architectures, mentor engineers, and deliver high-quality silicon for AI, HPC, and graphics products. This role blends hands-on design with technical leadership in a hybrid San Jose environment.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong RTL design and integration experience with Verilog/SystemVerilog.
• Experience with DFT for large-scale SoCs including scan and MBIST.

Responsibilities

• Define, implement, and verify DFT architectures and test features for complex SoCs.
• Drive scan insertion, ATPG generation, and test methodology development.
• Develop gate-level simulation strategies for ATPG pattern validation.
• Analyze test coverage and drive improvements in quality and yield.
• Collaborate with design, verification, and physical design teams for DFT implementation.
• Support silicon bring-up, manufacturing test, and failure analysis.

Skills

DFT architecture

RTL design

SystemVerilog

Technical leadership

Mentoring engineers

Education

Bachelor's or Master's degree in Electrical Engineering or related field

Tools

Synopsys DFT Compiler

TestMAX

PrimeTime

VCS

Cadence tool suites

Job description

AMD in San Jose seeks a Senior Staff Silicon Design Engineer to lead DFT strategy and bring-up across SoCs, collaborating with architecture, verification, physical design and manufacturing teams.

You will drive test architectures, mentor engineers, and deliver high-quality silicon for AI, HPC, and graphics products. This role blends hands-on design with technical leadership in a hybrid San Jose environment.