Senior ASIC Design Engineer: Front-End & DFT

Advanced Micro Devices; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD in San Jose, CA, is seeking a candidate to join the front-end design/integration team to deliver high-quality silicon and achieve first-pass silicon success. You will implement and verify DFT architectures and features, including scan insertion and ATPG pattern generation.

The ideal candidate will have strong communication and problem-solving skills, experience with DFT methodologies, and proficiency in Verilog RTL, scripting, and EDA tools.

Qualifications

• Understanding of Design-for-Test (DFT) methodologies.
• Experience with DFT verification tools and standards (IEEE 1500, JTAG 1149.x).
• Bachelor's or master's degree in a relevant engineering field.

Responsibilities

• Implementation and verification of DFT architecture and features
• Scan insertion and ATPG pattern generation
• Verification of ATPG patterns using gate-level simulation
• Test coverage and test cost reduction analysis
• Post-silicon support to accelerate yield learning

Skills

DFT methodologies

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Mentor TestKompress

Synopsys TetraMAX/DFTMAX

VCS

Perl scripting

Shell scripting

Verilog RTL

Job description

AMD in San Jose, CA, is seeking a candidate to join the front-end design/integration team to deliver high-quality silicon and achieve first-pass silicon success. You will implement and verify DFT architectures and features, including scan insertion and ATPG pattern generation.

The ideal candidate will have strong communication and problem-solving skills, experience with DFT methodologies, and proficiency in Verilog RTL, scripting, and EDA tools.