Senior Signal & Power Integrity Leader, Remote

Cisco Systems; Bellevue (WA); Hybrid; USD 214,000 - 310,000; Full time

Job summary

Cisco Silicon One seeks a senior Signal and Power Integrity Technical Leader to guide packaging development for next-generation ASICs. You will define rules for ultra-high-speed signaling, evaluate SI/PI across interposer, substrate, and PCB, and mentor a multidisciplinary team.

Leadership of packaging/ hardware integration and collaboration with system partners are key. This role offers onsite preference in San Jose with some remote flexibility.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of relevant signal and/or power integrity experience, or Master's degree with 8+ years, or PhD with 5+ years.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters.
• Hands‑on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Lead the Silicon Packaging SI team to define, design and verify ASIC packaging.
• Develop, document, and implement design rules for ultra-high-speed signaling.
• Analyze substrate signal integrity and power integrity, collaborating with layout for optimal solutions.
• Design, document, and develop ASIC packages for high-volume release with post-layout extraction.
• Define processes, methods, and tools for complex ASIC/package developments.

Skills

Signal integrity leadership

Power integrity

High-speed signaling

Team leadership

Communication

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Job description

Cisco Silicon One seeks a senior Signal and Power Integrity Technical Leader to guide packaging development for next-generation ASICs. You will define rules for ultra-high-speed signaling, evaluate SI/PI across interposer, substrate, and PCB, and mentor a multidisciplinary team.

Leadership of packaging/ hardware integration and collaboration with system partners are key. This role offers onsite preference in San Jose with some remote flexibility.