Remote Senior ASIC Packaging SI/PI Lead

Cisco; Atlanta (GA); Remote; USD 150,000 - 190,000; Full time

Job summary

Cisco Silicon One seeks a Signal and Power Integrity Technical Lead to advance next-generation ASIC packaging and verify ASIC packaging for Cisco platforms. You will define rules for ultra-high-speed signaling and collaborate with layout, system partners, and vendors to ensure power integrity and signal integrity goals are achieved.

You will mentor SI/PI teams, lead design reviews, and drive continuous improvement across multi-disciplinary engineering groups, shaping high-performance ASIC

Qualifications

• Bachelor's degree in Electrical Engineering or higher with 8+ years of related signal and power integrity experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience with high-speed signaling design and theory including 56G PAM4 SerDes architectures.
• Proficiency in SI/PI simulations using Cadence Sigrity, Ansys HFSS, Keysight ADS.
• Layout review and physical validation using Cadence APD and Ansys EM flows.
• Circuit analysis with SPICE for modeling and validation.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling meeting power, performance, and area goals.
• Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB solutions.
• Design, document, and develop ASIC packages for high-volume release including post-layout extraction.
• Lead cross-functional reviews with system partners to resolve complex SI/PI issues and define packaging workflows.
• Mentor junior engineers and drive continuous improvement across multi-disciplinary teams.
• Contribute to chip architecture discussions and high-performance ASIC design reviews.

Job description

Cisco Silicon One seeks a Signal and Power Integrity Technical Lead to advance next-generation ASIC packaging and verify ASIC packaging for Cisco platforms. You will define rules for ultra-high-speed signaling and collaborate with layout, system partners, and vendors to ensure power integrity and signal integrity goals are achieved.

You will mentor SI/PI teams, lead design reviews, and drive continuous improvement across multi-disciplinary engineering groups, shaping high-performance ASIC