Senior Signal & Power Integrity Tech Lead (Remote)

Cisco; Chicago (IL); Remote; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical/dental/vision insurance

401(k) with Cisco matching

Paid parental leave

Short and long-term disability

Basic life insurance

Stock grants/RSUs

Job summary

Cisco Silicon One in San Jose, CA is seeking a senior Signal and Power Integrity Technical Leader to guide packaging design and verification for next-generation ASICs. This role supports onsite work with some flexibility for remote arrangements.

You will mentor engineers, define SI/PI design rules, analyze SI/PI across interposer, substrate, and PCB, and collaborate with system partners to resolve complex issues using advanced rules. Strong leadership and hands-on lab experience are essential.

Qualifications

• Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant signal and/or power integrity experience, or PhD in Electrical Engineering and 5+ years of relevant signal and/or power integrity experience.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with a solid understanding of scattering and impedance network parameters.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
• Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
• Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
• Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.

Skills

Signal integrity

Power integrity

SerDes architectures

Channel modeling

BER prediction

Transmission line theory

Electromagnetics

Impedance networks

Package design

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Job description

Cisco Silicon One in San Jose, CA is seeking a senior Signal and Power Integrity Technical Leader to guide packaging design and verification for next-generation ASICs. This role supports onsite work with some flexibility for remote arrangements.

You will mentor engineers, define SI/PI design rules, analyze SI/PI across interposer, substrate, and PCB, and collaborate with system partners to resolve complex issues using advanced rules. Strong leadership and hands-on lab experience are essential.