Senior Signal & Power Integrity Lead - ASIC Packaging

Cisco Systems; Reno (NV); Remote; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical, dental, vision insurance

401(k) with Cisco matching

Paid parental leave

Disability coverage

Life insurance

Restricted stock units grants

Paid time off: holidays, vacation, and

Job summary

Cisco Systems is seeking a Lead Signal and Power Integrity technical leader for our Silicon One team in the US. You will head the SI/PI efforts for next-gen ASIC packaging, drive design rules for ultra-high-speed signaling, and collaborate across interposer, substrate, and PCB domains.

You will mentor engineers, drive post-layout extraction, and work with system partners to resolve complex SI/PI challenges, including 2.5D packaging considerations.

Qualifications

• Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 8+ years, or PhD with 5+ years of experience.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Lead the Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging for Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling meeting power/performance/area goals.
• Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction.
• Collaborate with system partners, vendors, and design leads to resolve complex technical issues using advanced technology design rules.
• Define processes, methods, and tools for the design and implementation of complex ASIC/package developments.
• Lead or participate in chip architecture discussions and design of high-performance ASICs including IC and analog/mixed-signal reviews.
• Mentor and support the SI team and packaging/hardware teams; promote design reviews and continuous improvement across teams.
• Develop and promote a culture of design reviews, postmortems, and continuous improvement.

Skills

Signal integrity

Power integrity

High-speed ASIC packaging

Tape-outs experience

BER prediction

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Job description

Cisco Systems is seeking a Lead Signal and Power Integrity technical leader for our Silicon One team in the US. You will head the SI/PI efforts for next-gen ASIC packaging, drive design rules for ultra-high-speed signaling, and collaborate across interposer, substrate, and PCB domains.

You will mentor engineers, drive post-layout extraction, and work with system partners to resolve complex SI/PI challenges, including 2.5D packaging considerations.