Senior ASIC Packaging SI/PI Lead (Hybrid/Remote)

Cisco Systems, Inc; Atlanta (GA); Hybrid; USD 166,000 - 308,000; Full time

Benefits offered by this job

Health insurance

401(k) plan with company match

Paid parental leave

Paid time off

Job summary

Cisco Silicon One is hiring a Signal and Power Integrity Technical Lead to help define, design, and verify ASIC packaging for Cisco platforms. You will drive ultra-high-speed signaling, perform SI/PI analyses, and lead cross‑functional teams across interposer, substrate, and PCB workstreams.

The role demands strong expertise in 56G PAM4 SerDes, layout validation, and collaboration with system partners. Remote work is considered, with an onsite preference in San Jose, CA or nearby locations.

Qualifications

• Bachelor's degree in Electrical Engineering required or equivalent.
• 8+ years in signal and power integrity for high‑speed channels.
• Experience with pre/post-layout SI/PI simulations and EDA tools.

Responsibilities

• Develop design rules for ultra-high-speed signaling to meet PPA goals.
• Analyze SI/PI for interposer, substrate, and PCB, coordinating with layout teams.
• Design and develop ASIC packages for high-volume, high-quality releases.
• Collaborate with partners to resolve complex design issues using advanced rules.
• Define processes, methods, and tools for complex ASIC/package developments.
• Lead or participate in chip architecture discussions for high‑performance ASICs.
• Mentor SI team and influence packaging/hardware teams.
• Promote design reviews, postmortems, and continuous improvement.

Skills

High-Speed Design & Theory

SI/PI Simulation Proficiency

Layout Review

Circuit Analysis

Transmission Line Theory

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM Flows

Job description

Cisco Silicon One is hiring a Signal and Power Integrity Technical Lead to help define, design, and verify ASIC packaging for Cisco platforms. You will drive ultra-high-speed signaling, perform SI/PI analyses, and lead cross‑functional teams across interposer, substrate, and PCB workstreams.

The role demands strong expertise in 56G PAM4 SerDes, layout validation, and collaboration with system partners. Remote work is considered, with an onsite preference in San Jose, CA or nearby locations.