Senior SI/PI Packaging Lead for 2.5D ASICs

Cisco; Dallas (TX); A distancia; USD 150.000 - 230.000; Jornada completa

Descripción de la vacante

Cisco Silicon One seeks a senior Signal and Power Integrity Technical Lead for remote-friendly US-based candidates. This role focuses on developing ASIC packaging, SI/PI analyses across interposer, substrate, and PCB, and leading high-speed designs in a global silicon architecture.

You will drive post-layout extraction, collaborate with vendors and design leads, mentor teammates, and shape processes for complex ASIC/package developments in a fast-paced environment.

Formación

• BS in Electrical Eng with 8+ years in SI/PI.
• Experience with 56G PAM4 SerDes architectures and BER prediction.
• Proficiency with Cadence Sigrity, HFSS, and Keysight ADS.
• Strong layout review and physical validation experience.

Responsabilidades

• Develop and document design rules for ultra-high-speed signaling.
• Analyze substrate SI and PI and collaborate with layout team.
• Design and develop ASIC packages for high-volume release with post-layout extraction.
• Collaborate with system partners and vendors to solve complex issues.
• Define processes, methods, and tools for ASIC/package design.
• Lead or participate in chip architecture discussions for high-performance ASICs.
• Mentor signal integrity team and other engineers.
• Promote design reviews, postmortems, and continuous improvement.

Conocimientos

High-Speed Design

SI/PI Simulation

Layout Review

Circuit Analysis

Power Integrity

Team Leadership

Educación

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Herramientas

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

SPICE

Descripción del empleo

Cisco Silicon One seeks a senior Signal and Power Integrity Technical Lead for remote-friendly US-based candidates. This role focuses on developing ASIC packaging, SI/PI analyses across interposer, substrate, and PCB, and leading high-speed designs in a global silicon architecture.

You will drive post-layout extraction, collaborate with vendors and design leads, mentor teammates, and shape processes for complex ASIC/package developments in a fast-paced environment.