Senior SI/PI Engineer: 2.5D/3D Packaging

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. is seeking a Sr. Signal & Power Integrity Engineer to lead packaging SI/PI analysis and optimization for next-generation machine learning and data center ASICs.

You will own the package-level SI/PI strategy from architecture trade-offs to design closure, measurement, and validation, interfacing with IC, package, and board teams to ensure performance and manufacturability.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 10+ years of experience in signal integrity, power integrity, and package design.
• Deep expertise in package SI/PI analysis: S-parameter extraction, PDN impedance analysis, IR drop, crosstalk, and return loss.
• Hands‑on with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent.

Responsibilities

• Lead package-level SI/PI analysis for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures.
• Design and optimize package stack-ups for high-speed and power delivery performance.
• Perform high-speed channel simulations for die-to-die and die-to-board interfaces through the package.
• Analyze and optimize the package PDN end-to-end: decoupling strategy, plane resonance, IR drop, and AC impedance.

Skills

S-parameter extraction

PDN impedance analysis

IR drop analysis

EM simulation

2.5D/3D packaging

Power integrity analysis

Clock distribution & jitter

Education

Bachelor's degree in Electrical Engineering

Master's degree (preferred)

Tools

HFSS

Cadence Sigrity (PowerSI, PowerDC, Clarity)

ADS

Ansys RedHawk-SC

Cadence Virtuoso

Job description

Annapurna Labs (U.S.) Inc. is seeking a Sr. Signal & Power Integrity Engineer to lead packaging SI/PI analysis and optimization for next-generation machine learning and data center ASICs.

You will own the package-level SI/PI strategy from architecture trade-offs to design closure, measurement, and validation, interfacing with IC, package, and board teams to ensure performance and manufacturability.