Senior IC Package Layout Engineer — 2.5D/3D-IC

Amazon Web Services (AWS); Tempe (AZ); On-site; USD 136,000 - 184,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. within AWS is seeking a Package Layout Design Engineer to advance IC packaging for AI/ML hardware. You will handle floor planning through tape-out, collaborating with SI/PI, thermal, and manufacturing to meet performance targets.

Role requires hands-on experience with package layout tools and a deep understanding of 2.5D/3D-IC, RDL, TSV, and interposer technologies. Great communication and teamwork are essential.

Qualifications

• Demonstrated experience in IC package layout and physical design
• Experience from concept to tape-out for multi-layer substrates or interposers
• Experience using package layout tools (Cadence, Synopsys, Mentor) and related DFM rules
• Ability to debug and verify at IP to full system level
• Familiarity with advanced packaging (2.5D/3D-IC, fan-out, RDL, TSV)

Responsibilities

• Execute package layout tasks from floor planning to tape out
• Implement physical designs for 2.5D, 3D-IC, and related packaging
• Support floorplan development including die placement and power routing
• Perform RDL, substrate routing, and interconnects for high-density layouts
• Coordinate with ASIC physical design teams for die-package interface
• Contribute to cross-level layout optimization and design rules
• Maintain package stack-up definitions with SI/PI teams
• Run DRC and connectivity checks and support design closure
• Collaborate with OSATs and foundries for DFM compliance
• Work with SI/PI engineers on impedance and shielding constraints

Skills

Electrical engineering foundations

IC package layout

Physical design

Bug identification

Multi-level verification

Packaging technologies

Power/ground plane design

Routing and DFM constraints

Collaboration across teams

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical or Communications Engineering or related field

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (U.S.) Inc. within AWS is seeking a Package Layout Design Engineer to advance IC packaging for AI/ML hardware. You will handle floor planning through tape-out, collaborating with SI/PI, thermal, and manufacturing to meet performance targets.

Role requires hands-on experience with package layout tools and a deep understanding of 2.5D/3D-IC, RDL, TSV, and interposer technologies. Great communication and teamwork are essential.