Senior IC Package Layout Engineer - 2.5D/3D Packaging

Amazon; Tempe (AZ); On-site; USD 159,000 - 215,000; Full time

Job summary

Amazon (Annapurna Labs) seeks a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for ML and data center ASICs.

You will own the package layout from floor planning through tape-out, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Join a team delivering production-ready designs with senior mentorship and cross‑functional collaboration.

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 10+ years of experience in IC package layout and physical design.
• Proven track record leading package designs from concept to tape-out.
• Hands-on with package layout tools: Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition.
• Deep knowledge of 2.5D/3D-IC, fan-out WLP, RDL, TSV, and silicon bridges.

Responsibilities

• Lead the full package layout cycle from die floor planning to tape-out release.
• Drive physical design of 2.5D/3D‑IC and advanced packaging architectures.
• Define floorplans, power/ground distribution, and high-speed routing strategies.
• Perform detailed RDL/substrate routing for high-density interconnects.
• Coordinate with ASIC design, OSATs, and foundries for DFM and manufacturability.
• Enforce design rules and run DRC/verification with design closure.
• Mentor junior engineers and contribute to automation and best practices.

Skills

Package layout leadership

IC package layout

Floor planning

RDL routing

Interposer/substrate design

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or equivalent

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Amazon (Annapurna Labs) seeks a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for ML and data center ASICs.

You will own the package layout from floor planning through tape-out, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Join a team delivering production-ready designs with senior mentorship and cross‑functional collaboration.