Lead IC Package Layout Engineer — 2.5D/3D-IC

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. seeks a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next-generation ML and data center ASICs.

You will own the package layout from floor planning through tape out and manufacturing release, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Responsibilities include overseeing 2.5D/3D-IC packaging, flow planning, DFM, and cross‑level optimization across die,

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 10+ years of experience in IC package layout and physical design.
• Proven track record leading package designs from concept through tape out.

Responsibilities

• Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
• Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out WLP, and silicon bridge interconnects.
• Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high-speed signal routing, and decoupling capacitor placement.
• Perform detailed RDL and substrate routing for high-density interconnects across multi-layer substrates and interposers.
• Coordinate die-level RDL routing and bump planning with ASIC physical design teams for power delivery and signal routing.
• Drive cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels for best PDN and signaling performance.
• Develop and maintain package stack-up definitions with impedance targets and manufacturing constraints.
• Create and enforce package design rules with OSATs to ensure DFM and high yield.
• Run and review DRC and connectivity checks; drive design closure with zero escapes.
• Manage package design schedules, milestones, and deliverables across multiple projects.
• Collaborate with SI/PI engineers to incorporate electrical constraints into layout.
• Interface with OSAT vendors and foundries on manufacturing feasibility and process capability.
• Identify packaging risks early and propose mitigations for reliability and manufacturability.
• Mentor junior layout engineers and contribute to best practices and automation flows.

Skills

Packaging expertise

Team leadership

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or equivalent

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (U.S.) Inc. seeks a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next-generation ML and data center ASICs.

You will own the package layout from floor planning through tape out and manufacturing release, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Responsibilities include overseeing 2.5D/3D-IC packaging, flow planning, DFM, and cross‑level optimization across die,