Senior Signal & Power Integrity Engineer – 2.5D/3D-IC Packaging

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 157,000 - 213,000; Full time

Benefits offered by this job

Health insurance

RSUs supporting compensation

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs (U.S.) Inc. is recruiting a Signal or Power Integrity Engineer to advance SI/PI analysis for next-gen machine learning and data center ASICs.

You will work on package-level SI/PI, 2.5D/3D-IC, and interposer architectures, collaborating with SoC and board teams to meet performance and power targets. You will develop and validate models for decoupling, manage stack-up and impedance, and run high-speed simulations to guide design decisions.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of experience in signal integrity, power integrity, or package design.
• Solid understanding of either SI (S-parameter extraction, crosstalk, return loss, channel analysis) or PI (PDN impedance analysis, IR drop, decoupling strategy).
• Experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent.
• Understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects.
• Familiarity with stack-up design and impedance control for multi-layer substrates or silicon interposers.
• Good communication skills across silicon, package, and board teams.

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures under guidance from senior engineers.
• Support package stack-up design: assist with dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies.
• Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces, or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance).
• Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths.
• Build and validate models for decoupling technologies such as on-die capacitance, deep trench capacitors (DTCs), or IPD capacitors as needed.
• Coordinate with SoC die-level teams and board design teams to gather requirements and support co-optimization of package architecture.
• Flag potential package manufacturing risks - warpage, via reliability, impedance variation - and propose mitigation approaches.

Skills

SI/PI analysis

DFE/CTLE/FFE techniques

HFSS

Sigrity (PowerSI/PowerDC/Clarity)

ADS

2.5D/3D-IC packaging

PDN impedance analysis

communication in cross-team

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering

Tools

HFSS

Cadence Sigrity

ADS

Job description

Annapurna Labs (U.S.) Inc. is recruiting a Signal or Power Integrity Engineer to advance SI/PI analysis for next-gen machine learning and data center ASICs.

You will work on package-level SI/PI, 2.5D/3D-IC, and interposer architectures, collaborating with SoC and board teams to meet performance and power targets. You will develop and validate models for decoupling, manage stack-up and impedance, and run high-speed simulations to guide design decisions.