IC Package Layout Engineer: 2.5D/3D Packaging

Amazon; Tempe (AZ); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon's Annapurna Labs hardware team seeks a Package Layout Design Engineer to advance the physical design of IC packages for ML and data center ASICs. You will drive tasks from floor planning to tape-out, collaborating with SI/PI, thermal, and manufacturing teams to meet performance and reliability targets.

You will implement architectures including 2.5D interposers and 3D-ICs, ensuring DFM compliance and robust routing across multi-layer substrates.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years in IC package layout and physical design.
• Experience executing package designs from concept to tape out for multi-layer substrates or silicon interposers.
• Hands-on experience with package layout tools (Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition).
• Understanding of 2.5D/3D-IC, fan-out WLP, RDL, TSV, and related interconnects.
• Working knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity).
• Experience with bump map and ball map definition, escape routing, and power/ground plane design.
• Good communication across design, SI/PI, and manufacturing teams.

Responsibilities

• Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Implement physical designs for 2.5D interposer, 3D-IC, fan‑out packaging, and silicon bridge technologies.
• Support floorplan development considering die placement, bump maps, power/ground distribution, signal routing, and decoupling capacitors.
• Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias.
• Support die-level RDL routing and bump planning with ASIC Physical Design teams.
• Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels.
• Assist in maintaining package stack-up definitions with SI/PI and materials teams.
• Run physical verification checks (DRC, connectivity, shorts/opens).
• Follow and refine package design rules with OSAT partners and foundries for DFM compliance.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the layout.

Skills

IC packaging

Physical design

Package design tools

Advanced packaging

DFM constraints

Bump map definition

Communication skills

Education

Bachelor's in Electrical Eng

MS in IC packaging (preferred)

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Amazon's Annapurna Labs hardware team seeks a Package Layout Design Engineer to advance the physical design of IC packages for ML and data center ASICs. You will drive tasks from floor planning to tape-out, collaborating with SI/PI, thermal, and manufacturing teams to meet performance and reliability targets.

You will implement architectures including 2.5D interposers and 3D-ICs, ensuring DFM compliance and robust routing across multi-layer substrates.