SI/PI Engineer for 2.5D/3D-IC Packaging

Socket.dev; Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

Annapurna Labs, within Amazon, is seeking a Signal or Power Integrity Engineer to advance SI/PI analysis for next‑gen 2.5D/3D‑IC packaging in data center ASICs. You will perform simulations, build models, and help shape die‑to‑board interfaces while aligning with IC and board teams.

Responsibilities include high‑speed channel simulations, stack‑up design support, and mitigation of packaging risks, with mentorship from senior engineers and a focus on scalable hardware solutions.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of experience in signal integrity, power integrity, or package design.
• Solid understanding of either SI (S-parameter extraction, crosstalk, return loss, channel analysis) or PI (PDN impedance analysis, IR drop, decoupling strategy).
• Experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent.
• Understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects.
• Familiarity with stack-up design and impedance control for multi-layer substrates or interposers.

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and interposer architectures.
• Support package stack-up design: dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies.
• Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces.
• Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces.
• Build and validate models for decoupling technologies such as on-die capacitance, deep trench capacitors or IPD capacitors.
• Coordinate with SoC die-level teams and board design teams to gather requirements and support co-optimization of package architecture.
• Flag potential package manufacturing risks - warpage, via reliability, impedance variation - and propose mitigation approaches.

Skills

Signal integrity

Power integrity

Package design

EM simulation

2.5D/3D-IC

Channel analysis

Crosstalk

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

HFSS

Cadence Sigrity PowerSI

PowerDC

ADS

Job description

Annapurna Labs, within Amazon, is seeking a Signal or Power Integrity Engineer to advance SI/PI analysis for next‑gen 2.5D/3D‑IC packaging in data center ASICs. You will perform simulations, build models, and help shape die‑to‑board interfaces while aligning with IC and board teams.

Responsibilities include high‑speed channel simulations, stack‑up design support, and mitigation of packaging risks, with mentorship from senior engineers and a focus on scalable hardware solutions.