Senior SerDes Architect: High-Speed I/O & 224G Links

Intel Corporation; Santa Clara (CA); On-site; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel Corporation's Advanced Design Foundational IP Organization seeks a senior SerDes expert to own link architecture and transistor‑level design for next‑gen high‑speed interfaces. You will drive system models, perform link budgeting, and lead silicon bring‑up across TX/RX, clocking, and power integrity in collaboration with design, layout and test teams.

Leadership in design reviews, mentoring, and cross‑functional coordination with process development completes the profile for this on‑site

Qualifications

• Minimum qualifications include 6+ years of high-speed SerDes experience or 4+ years with a Master’s or 2+ years with a PhD.
• Experience in transistor-level SerDes TX/RX/clocking at 28 Gb/s per lane or higher.
• Proficiency in link architecture analysis, lab validation, and MATLAB/Python modeling.

Responsibilities

• Define SerDes link architecture for next-gen interfaces (224G/448G PAM4, PCIe Gen7/Gen8, UCIe).
• Build and maintain system-level link models and derive block-level specs.
• Lead transistor-level design of TX/RX/clocking blocks and perform silicon bring-up.
• Drive test-chip definition, tapeout readiness, and correlate measurements to models.
• Provide technical leadership and mentor engineers across teams.

Skills

High-speed SerDes design

SerDes system architecture

Transistor-level design

MATLAB/Python modeling

Link modeling & analysis

Education

Bachelors in Electrical Engineering or related

Master’s degree in Electrical Engineering

Ph.D. in Electrical Engineering

Tools

MATLAB

Python

Job description

Intel Corporation's Advanced Design Foundational IP Organization seeks a senior SerDes expert to own link architecture and transistor‑level design for next‑gen high‑speed interfaces. You will drive system models, perform link budgeting, and lead silicon bring‑up across TX/RX, clocking, and power integrity in collaboration with design, layout and test teams.

Leadership in design reviews, mentoring, and cross‑functional coordination with process development completes the profile for this on‑site