Principal SerDes Design Engineer

Celero Communications, Inc.; United States; Remote; USD 180,000 - 260,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to architect and implement next‑generation SerDes for high-speed interconnects powering AI workloads.

The role involves system-level modeling, behavioral simulations, and leading lab validation in a state‑of‑the‑art lab. Ideal candidates hold a Master’s or PhD in EE with 10+ years of SerDes experience, proven tape-out success, and deep knowledge of 16nm–2nm processes.

Qualifications

• 10+ years in SerDes design with tape-out experience.
• Strong in lab bring-up, characterization, and debugging for production.
• Experience with advanced node technologies (16nm/12nm through 2nm).
• Cross-functional collaboration to deliver IP within SOCs.

Responsibilities

• Define architecture and topologies for next‑gen SerDes.
• Lead system-level modeling and jitter budgeting using MATLAB/Verilog-A.
• Design analog/mixed-signal blocks (CTLE, DFE, PLLs, DLLs, TDCs).
• Oversee layout to minimize parasitics and electromigration; validate SI/PI.

Skills

SerDes design

High speed signaling

SystemVerilog

MATLAB

Education

Master’s or PhD in Electrical Engineering

Tools

SystemVerilog

Verilog-A

MATLAB

Job description

Principal SerDes Design Engineer

About the job

We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do

• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills

celerocatsone

Javier Leon
Talent Acquisition
619-227-3193 cell/text
[e-mail]
www.celero.inc