Lead, High-Speed SerDes Design (224G/448G IPs)

Eliyan Corporation; San Francisco (CA); On-site; USD 170,000 - 220,000; Full time

Job summary

Eliyan Corporation in San Francisco seeks a SerDes Digital Design Lead to drive architecture for next-generation high-speed serial link IPs targeting 224G and 448G data rates. The role involves leading digital design for both transmitter and receiver datapaths while collaborating with cross-functional experts to innovate in high-performance products.

Suitable candidates will hold a Masters or Ph.D in Electrical Engineering with over 12 years in digital design, showcasing deep knowledge in SerDes architectures and RTL design skills.

Qualifications

• 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs.
• Strong understanding of synthesis, timing closure, CDC/RDC, and DFT methodologies.
• Demonstrated technical leadership and ability to mentor engineers.

Responsibilities

• Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks.
• Design and optimize PHY-level digital logic including TX driver control and RX datapath.
• Collaborate closely with analog designers on SerDes AFE integration and AMS co-simulation.

Skills

RTL design skills in SystemVerilog

Expert-level knowledge of SerDes DSP architectures

Hands-on experience with high-speed digital design

Strong working knowledge of IEEE 802.3 specifications

Experience with optical/electrical interconnects

Education

Masters or Ph.D in Electrical Engineering or Computer Engineering

Job description

Eliyan Corporation in San Francisco seeks a SerDes Digital Design Lead to drive architecture for next-generation high-speed serial link IPs targeting 224G and 448G data rates. The role involves leading digital design for both transmitter and receiver datapaths while collaborating with cross-functional experts to innovate in high-performance products.

Suitable candidates will hold a Masters or Ph.D in Electrical Engineering with over 12 years in digital design, showcasing deep knowledge in SerDes architectures and RTL design skills.