SerDes Digital Design Lead - High-Speed IP Architect

Eliyan; San Francisco (CA); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Excellent benefits

Fun work environment

Job summary

A leading chiplet startup is seeking a SerDes Digital Design Lead to drive architecture and implementation of high-speed serial link IPs targeting 224G and 448G data rates. You will work on digital logic for cutting-edge interconnect products within a collaborative, innovative environment. The ideal candidate has over 12 years of experience in digital design, a Master's or Ph.D. in Electrical Engineering, and strong RTL design skills. This role offers a great work environment and excellent benefits.

Qualifications

• 12+ years of experience in digital design of high-speed SerDes or related IP.
• Strong hands-on experience with high-speed digital design on advanced process nodes.
• Experience working at the digital-analog boundary.

Responsibilities

• Lead the micro-architecture definition and RTL implementation.
• Collaborate closely with analog/mixed-signal designers.
• Own design deliverables from RTL development through tapeout signoff.
• Develop power-efficient digital architectures.

Skills

RTL design skills in SystemVerilog

Knowledge of SerDes DSP architectures

Experience with IEEE 802.3 specifications

Technical leadership and mentoring

Education

Masters or Ph.D in Electrical Engineering

Job description

A leading chiplet startup is seeking a SerDes Digital Design Lead to drive architecture and implementation of high-speed serial link IPs targeting 224G and 448G data rates. You will work on digital logic for cutting-edge interconnect products within a collaborative, innovative environment. The ideal candidate has over 12 years of experience in digital design, a Master's or Ph.D. in Electrical Engineering, and strong RTL design skills. This role offers a great work environment and excellent benefits.