Senior SerDes Analog Design

Mulya Technologies; Austin (TX); Hybrid; USD 120,000 - 150,000; Full time

Job summary

Mulya Technologies is in Austin, Texas, seeking a SerDes Analog Designer to develop cutting-edge circuits and architectures for ultra-high-speed wireline communication systems. The role involves driving transistor-level designs from specification to market introduction.

The ideal candidate will have over 10 years of experience in high-performance analog or mixed-signal IC development, strong analytical skills, and proficiency in Cadence tools.

Qualifications

• 10+ years of experience in high‑performance analog or mixed‑signal IC development in advanced CMOS processes.
• Strong understanding of transistor‑level circuit design including noise and mismatch analysis.
• Experience with evaluating silicon on bench and familiarity with standard lab equipment.

Responsibilities

• Develop cuttings circuits and architectures for ultra‑high speed wireline communication systems.
• Drive the development of high performance transistor level design from initial specification to market introduction.

Skills

High‑performance analog or mixed‑signal IC development

High‑speed analog design and building block circuits for SERDES

Evaluating silicon on bench

Transistor‑level circuit design

Cadence schematic capture

Layout parasitic extraction

Tools

Cadence Virtuoso

HSPICE

MATLAB

Job description

SerDes Analog Designer (Hybrid)

SerDes analog designer focusing 100Gbps+ wireline technologies (TX and RX path). The successful candidate in this role will develop cutting‑edge circuits and architectures for ultra‑high speed wireline communication systems, and will drive the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market.

Qualifications

• 10+ years of experience in high‑performance analog or mixed‑signal IC development in advanced CMOS processes
• Familiarity with high‑speed analog design and building block circuits for SERDES technology such as ADC/DAC, CTLE, CDR, PLL etc.
• Must have a track record of successfully taking designs to production
• Ability to work with customers to define products that address needs
• Must have experience with evaluating silicon on bench and familiarity with standard lab equipment
• Strong intuitive and analytical understanding of transistor‑level circuit design including noise and mismatch analysis
• Experience with analog and digital behavioural modeling, and/or synthesis of digital control blocks
• Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
• MATLAB understanding would be preferred but not mandatory
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process
• Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes
• Must be able to work independently, create and adhere to schedules
• Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations