Senior Distinguished Circuit Engineer - HSIO/SerDes Lead

Ampere Computing LLC; Durham (NC); On-site; USD 280,000 - 420,000; Full time

Benefits offered by this job

Health insurance

401(k) retirement plan

Unlimited flextime

Paid holidays

Job summary

Ampere Computing LLC is seeking a Distinguished Circuit Engineer to steer High-Speed I/O and SerDes development for next-gen server SoCs. You will own the technical roadmap, collaborate with system architects, packaging, and validation teams, and drive end-to-end IP integration from spec to production.

You will mentor engineers, influence external IP partners, and lead post-silicon validation, with ownership of critical analog/mixed-signal architectures across 3nm/2nm processes.

Qualifications

• Significant leadership experience in high-speed SerDes/mixed-signal PHY silicon development.
• Proven track record of bringing high-speed SerDes (PAM4/NRZ, D2D, PCIe, DDR, or UCIe) to production on advanced nodes.
• Deep expertise in analog/mixed-signal circuit architectures and timing/electrical specs.

Responsibilities

• Architect and guide proprietary SerDes and D2D PHY IP development.
• Lead engagement with external IP vendors and foundries; drive make-vs-buy decisions.
• Define and integrate detailed IP electrical, functional, and timing specifications with SoC teams.
• Mentor engineers and align roadmaps with leadership and cross-functional groups.
• Lead post-silicon validation and debugging for high-speed interfaces.

Skills

SerDes leadership

Mixed-signal design

Cross-functional leadership

SoC integration

Education

Electrical or Computer Engineering degree (Bachelors 15y / Masters 12y / PhD 8y)

Tools

Cadence Virtuoso

Spectre/CustomSim

Synopsys PrimeSim/FineSim

Job description

Ampere Computing LLC is seeking a Distinguished Circuit Engineer to steer High-Speed I/O and SerDes development for next-gen server SoCs. You will own the technical roadmap, collaborate with system architects, packaging, and validation teams, and drive end-to-end IP integration from spec to production.

You will mentor engineers, influence external IP partners, and lead post-silicon validation, with ownership of critical analog/mixed-signal architectures across 3nm/2nm processes.