Senior SerDes Architect – High-Speed Analog & Mixed-Signal

Intel Corporation; Hillsboro (OR); On-site; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation is seeking a Senior Analog and Mixed Signal Design Engineer in Hillsboro, OR to own SerDes link architecture and transistor-level design of critical analog front-end and clocking blocks. You will build system models, lead tapeout readiness, and validate performance against models in a senior IC design team.

The role emphasizes 28 Gb/s+ SerDes experience, lab validation, and cross-functional collaboration across design, layout, and measurement engineers.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering.
• 6+ years of industry experience in high-speed SerDes circuit design.
• Experience in transistor-level design of SerDes TX/RX or clocking circuits on silicon at 28 Gb/s per lane or higher.
• Experience in SerDes link architecture, channel and link-budget analysis, or equalization studies.
• Lab validation of high-speed links and correlation of BER/eye/jitter to simulations.
• Behavioral or statistical link modeling in MATLAB or Python.

Responsibilities

• Define SerDes link architecture for next-generation interfaces and provide channel analysis and equalization strategy.
• Build and maintain system-level link models and derive block-level specifications for TX/RX/CLK circuits.
• Lead transistor-level design of critical SerDes blocks (TX drivers, RX front ends, DFE, ADCs, clocking).
• Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; analyze silicon-to-model gaps.
• Translate SerDes requirements into process/PDK requirements and drive design-technology co-optimization.
• Provide technical leadership, mentor engineers, and lead design reviews.

Skills

SerDes design

Link architecture

Lab validation

Modeling MATLAB/Python

Transistor-level design

Clocking circuits

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

MATLAB

Python

IBIS-AMI

Job description

Intel Corporation is seeking a Senior Analog and Mixed Signal Design Engineer in Hillsboro, OR to own SerDes link architecture and transistor-level design of critical analog front-end and clocking blocks. You will build system models, lead tapeout readiness, and validate performance against models in a senior IC design team.

The role emphasizes 28 Gb/s+ SerDes experience, lab validation, and cross-functional collaboration across design, layout, and measurement engineers.