Senior SerDes IP Physical Design Lead

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 190,000 - 270,000; Full time

Job summary

Synopsys, Inc. seeks an experienced engineer to own physical integration for high-speed SerDes IP (56G/112G/224G PAM4/6) from floorplanning to GDSII. You will drive timing closure, power optimization, and signoff at 16nm and below, coordinating with front-end, analog, and CAD teams to assure robust tapeouts.

You will lead customer engagements on SOC-level integration planning, build and improve constraints and flows, mentor teammates, and help shape next-generation SerDes architectures.

Qualifications

• 10+ years in digital or physical SerDes design.
• Deep RTL-to-GDSII experience and chip-level integration.
• Experience with FinFET nodes (16nm or below) and low-power techniques.
• Strong scripting skills in Perl, Tcl, Python.

Responsibilities

• Own physical integration for advanced SerDes IP from floorplanning through GDSII.
• Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 across FinFET nodes.
• Develop timing constraints, clock architectures, and low-power design techniques.
• Lead customer engagements on physical integration topics, including tapeout support.
• Build and improve design methodologies, automation scripts, and flows that reduce customer effort.
• Debug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams.
• Mentor engineers across the team on physical design best practices.

Skills

Digital/physical design

Timing closure

FinFET node knowledge

Scripting: Perl, Tcl, Python

Customer communication

Education

MSEE with 10+ years

BSEE with 12+ years

Tools

Perl

Tcl

Python

RTL-to-GDSII flow

Job description

Synopsys, Inc. seeks an experienced engineer to own physical integration for high-speed SerDes IP (56G/112G/224G PAM4/6) from floorplanning to GDSII. You will drive timing closure, power optimization, and signoff at 16nm and below, coordinating with front-end, analog, and CAD teams to assure robust tapeouts.

You will lead customer engagements on SOC-level integration planning, build and improve constraints and flows, mentor teammates, and help shape next-generation SerDes architectures.