Senior RTL Verification Engineer - UVM/SystemVerilog

Delos Data Inc; Oregon; Hybrid; USD 160,000 - 240,000; Full time

Benefits offered by this job

Equity

401(k) plan

Benefits package

Job summary

Delos Data Inc is seeking an experienced RTL Verification Engineer to ensure functionality and quality of complex digital designs across ASIC/FPGA platforms. You will build robust verification environments, run coverage-driven plans, and collaborate closely with RTL designers to deliver reliable silicon.

The ideal candidate will have deep hands-on SystemVerilog/UVM experience, modern verification workflows, and the ability to drive verification efforts from planning through closure.

Qualifications

• 7+ years of digital design verification experience.
• Strong hands-on SystemVerilog/UVM experience and modern verification workflows.
• Experience with coverage-driven verification and testbench development.

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM or equivalent.
• Create and execute coverage-driven verification plans aligned with design specifications.
• Develop directed and constrained-random test cases and sequences.
• Analyze simulation results, debug verification and design issues, and perform root-cause analysis.
• Implement and track functional and code coverage, driving verification to closure.
• Develop reusable verification components and write SystemVerilog Assertions (SVA).
• Participate in design and verification reviews for testability and correctness.
• Automate regression testing and enhance verification infrastructure using Python/scripting.
• Contribute to continuous improvement of verification processes, tools, and methodologies.

Skills

UVM-based verification

SystemVerilog

Python scripting

AXI/AXI-S/APB protocols

PCIe / Ethernet / SPI / I2C protocols

Debug & root-cause analysis

Verification planning

Regression automation

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

Job description

Delos Data Inc is seeking an experienced RTL Verification Engineer to ensure functionality and quality of complex digital designs across ASIC/FPGA platforms. You will build robust verification environments, run coverage-driven plans, and collaborate closely with RTL designers to deliver reliable silicon.

The ideal candidate will have deep hands-on SystemVerilog/UVM experience, modern verification workflows, and the ability to drive verification efforts from planning through closure.