Senior RTL Verification Engineer | UVM, SystemVerilog, PCIe

Delos Data Inc.; United States; Hybrid; USD 160,000 - 240,000; Full time

Benefits offered by this job

Equity

401(k)

Job summary

Delos Data Inc. is seeking an experienced RTL Verification Engineer to ensure the correctness of complex digital designs across ASIC and FPGA platforms.

You will build robust verification environments and drive coverage-driven verification plans. Key responsibilities include creating UVM-based environments, debugging intricate issues, and automating regression tests with Python while improving verification infrastructure.

Qualifications

• 7+ years of digital design verification experience with strong UVM and SystemVerilog skills.
• Experience with EDA tools like Synopsys VCS, Mentor Questa, or Cadence Xcelium and protocols like PCIe, Ethernet, AXI.

Responsibilities

• Develop and maintain UVM-based verification environments, creating directed and constrained-random test cases.
• Analyze simulation results, debug complex issues, and track functional/code coverage to closure.
• Automate regression testing with Python and enhance verification infrastructure.

Skills

UVM verification

SystemVerilog

Python

Regression testing

Coverage analysis

ASIC/FPGA verification

Digital design

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

Job description

Delos Data Inc. is seeking an experienced RTL Verification Engineer to ensure the correctness of complex digital designs across ASIC and FPGA platforms.

You will build robust verification environments and drive coverage-driven verification plans. Key responsibilities include creating UVM-based environments, debugging intricate issues, and automating regression tests with Python while improving verification infrastructure.