Senior RTL Verification Engineer — UVM/SystemVerilog, Equity

Delos Data Inc; United States; Hybrid; USD 160,000 - 240,000; Full time

Benefits offered by this job

Equity

401(k) plan

Benefits

Job summary

Delos Data Inc. is seeking an experienced RTL Verification Engineer to ensure the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms.

You will build robust verification environments and drive coverage-driven verification from planning through closure. The ideal candidate has deep hands-on SystemVerilog, UVM, and Python experience, and can collaborate with RTL designers to deliver reliable silicon.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or a related field.
• 7+ years of digital design verification experience.
• Strong hands-on with SystemVerilog, UVM, and Python.

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases
• Analyze simulation results, debug verification and design issues, and perform root-cause analysis with RTL engineers
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews, informing testability and optimization
• Automate regression testing and enhance verification infrastructure using Python and scripting
• Contribute to continuous improvement of verification processes, tools, and methodologies

Skills

UVM

SystemVerilog

Python

Verification plans

SVA

Education

Bachelor’s or Master’s in EE/CE

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

Job description

Delos Data Inc. is seeking an experienced RTL Verification Engineer to ensure the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms.

You will build robust verification environments and drive coverage-driven verification from planning through closure. The ideal candidate has deep hands-on SystemVerilog, UVM, and Python experience, and can collaborate with RTL designers to deliver reliable silicon.