Senior RTL Verification Engineer — SystemVerilog & UVM

Delos Data Inc; Palo Alto (CA); Hybrid; USD 160,000 - 240,000; Full time

Job summary

Delos Data Inc. in Silicon Valley is seeking an experienced RTL Verification Engineer to ensure the functionality of complex digital designs for ASIC/FPGA platforms.

You will build robust verification environments, implement coverage-driven plans, and collaborate with RTL designers to deliver reliable silicon. The ideal candidate has hands-on SystemVerilog, UVM, and Python experience and will drive verification from planning through closure.

Qualifications

• Bachelor’s or Master’s degree required in Electrical/Computer/Computer Engineering or related field
• 7+ years of digital design verification experience
• Proficiency in SystemVerilog, UVM, and Python
• Experience with industry-standard EDA tools (e.g., VCS, Questa, Xcelium) and verification methodologies

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases
• Analyze simulation results, debug verification and design issues, and perform root-cause analysis with RTL engineers
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews for testability and optimization
• Automate regression testing and enhance verification infrastructure using Python and scripting
• Contribute to continuous improvement of verification processes, tools, and methodologies

Skills

SystemVerilog

UVM

Python

Analytical skills

Communication

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

Job description

Delos Data Inc. in Silicon Valley is seeking an experienced RTL Verification Engineer to ensure the functionality of complex digital designs for ASIC/FPGA platforms.

You will build robust verification environments, implement coverage-driven plans, and collaborate with RTL designers to deliver reliable silicon. The ideal candidate has hands-on SystemVerilog, UVM, and Python experience and will drive verification from planning through closure.