Senior RTL Design Engineer - Hybrid AI Accelerator

Delos Data Inc; Palo Alto (CA); Hybrid; USD 160,000 - 240,000; Full time

Benefits offered by this job

Equity

401(k)

Benefits

Job summary

Delos Data Inc in Silicon Valley is seeking a Senior RTL Design Engineer to translate architectural specs into scalable RTL using Verilog/SystemVerilog. You will collaborate across architecture, verification, and physical design teams to optimize performance, power, and area.

We value deep digital design fundamentals, hands-on experience with RTL, and a track record of delivering production-ready blocks. This role blends independent work with cross-functional teamwork in a hybrid setting.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of RTL design experience.
• Strong hands-on Verilog/SystemVerilog skills.
• Solid digital design fundamentals and microarchitecture knowledge.
• Experience with simulation and debugging tools (VCS, Questa, Verdi, DVE).

Responsibilities

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog.
• Translate architectural specifications into scalable microarchitectures.
• Collaborate with architecture, verification, and physical design teams.
• Develop reusable RTL with high coding standards and documentation.
• Perform linting, CDC analysis, and ensure synthesis readiness.
• Support integration and debugging in simulation and early silicon.
• Participate in design reviews and discuss architecture tradeoffs.
• Work with verification teams to ensure functional coverage.
• Assist in timing closure and support backend teams.
• Contribute to design methodology improvements.

Skills

RTL design

Verilog/SystemVerilog

Education

Bachelor’s/Master’s in Electrical or Computer Engineering

Tools

VCS

Questa

Verdi

DVE

Job description

Delos Data Inc in Silicon Valley is seeking a Senior RTL Design Engineer to translate architectural specs into scalable RTL using Verilog/SystemVerilog. You will collaborate across architecture, verification, and physical design teams to optimize performance, power, and area.

We value deep digital design fundamentals, hands-on experience with RTL, and a track record of delivering production-ready blocks. This role blends independent work with cross-functional teamwork in a hybrid setting.