Senior RTL/SoC Verification Engineer

Core ASIC Inc; San Diego (CA); On-site; USD 130,000 - 190,000; Full time

Job summary

Core ASIC Inc in San Diego seeks an experienced RTL Verification engineer with 5 to 15 years in SystemVerilog and UVM. You will verify complex SoCs, drive functional verification, and collaborate across design, test, and firmware teams to ensure quality tape-outs.

The role requires strong knowledge of AMBA protocols and high-speed interfaces, experience with Synopsys/Cadence tools, and scripting for automation.

Qualifications

• Strong functional verification skills for complex SoCs.
• Solid RTL design expertise and review of synthesizable RTL.
• Proficiency in formal verification techniques and tools.
• Good understanding of pipelines, caches, buses and memory subsystems.
• Experience with SystemVerilog, UVM or similar frameworks.
• Familiarity with simulation, coverage and regression infrastructures; scripting in Python/Perl/shell.

Skills

Functional verification

RTL design

Formal verification

Computer architecture

SystemVerilog/UVM

Simulation/coverage/regression

Cross-functional teamwork

IP verification/VIP/Emulation

Education

Bachelors or Masters in Electrical/ Electronics/ Computer Engineering

Tools

Synopsys

Cadence

Job description

Core ASIC Inc in San Diego seeks an experienced RTL Verification engineer with 5 to 15 years in SystemVerilog and UVM. You will verify complex SoCs, drive functional verification, and collaborate across design, test, and firmware teams to ensure quality tape-outs.

The role requires strong knowledge of AMBA protocols and high-speed interfaces, experience with Synopsys/Cadence tools, and scripting for automation.