Senior RTL Design Engineer — Hybrid (Remote/On-site)

Delos Data Inc; Oregon; Hybrid; USD 160,000 - 240,000; Full time

Benefits offered by this job

Equity

401(k)

Health benefits

Job summary

Delos Data Inc is seeking a Senior RTL Design Engineer to translate architectural specs into scalable RTL, focusing on performance and power. You’ll work with architecture, verification, and physical design to deliver high-quality silicon blocks.

The role requires deep Verilog/SystemVerilog experience, strong digital design fundamentals, and the ability to drive design closure across the full lifecycle in a fast-growing AI data center context.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of RTL design experience.
• Strong Verilog/SystemVerilog hands-on experience.
• Solid digital design fundamentals and microarchitecture principles.
• Experience with simulation, linting, and timing analysis.

Responsibilities

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog.
• Translate architecture specs into scalable microarchitectures.
• Collaborate with architecture, verification, and physical design teams.
• Develop reusable RTL with coding standards and documentation.
• Perform linting, CDC analysis, and ensure synthesis readiness.
• Support RTL integration and debugging in simulation and early silicon.
• Participate in design reviews and discuss tradeoffs.
• Ensure functional coverage with verification teams.
• Assist timing closure and support backend teams.
• Contribute to design methodology improvements.

Skills

RTL design

Verilog

SystemVerilog

Digital design

Independent work

Education

Bachelor's or Master's in Electrical Engineering

Tools

VCS

Questa

Verdi

DVE

Job description

Delos Data Inc is seeking a Senior RTL Design Engineer to translate architectural specs into scalable RTL, focusing on performance and power. You’ll work with architecture, verification, and physical design to deliver high-quality silicon blocks.

The role requires deep Verilog/SystemVerilog experience, strong digital design fundamentals, and the ability to drive design closure across the full lifecycle in a fast-growing AI data center context.