Senior RTL Design Engineer for AI Accelerator Systems

Delos Data; Palo Alto (CA); On-site; USD 160,000 - 240,000; Full time

Job summary

Delos Data is seeking a Senior RTL Design Engineer to design, implement, and deliver high-quality RTL for complex digital systems in our Palo Alto office. You will translate architectural specs into scalable microarchitectures using Verilog/SystemVerilog, collaborating with architecture, verification, and physical design teams to meet timing, power, and area goals.

Ideal candidates have 5+ years in RTL design, strong design fundamentals, and hands-on experience with synthesis, linting, and

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in RTL design.
• Strong hands‑on experience with Verilog/SystemVerilog.
• Solid understanding of synchronous digital design and microarchitecture principles.
• Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE).
• Familiarity with synthesis, timing, and physical design constraints.
• Strong analytical and problem‑solving skills.
• Clear written and verbal communication skills for cross‑functional collaboration.
• High attention to detail and ability to deliver high‑quality design outcomes.
• Ability to work independently and manage tasks to completion, including AI‑assisted workflows.

Responsibilities

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog.
• Translate architectural specifications into clean, efficient, and scalable microarchitectures.
• Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure.
• Develop high-quality, reusable RTL with strong coding standards and documentation.
• Perform linting, CDC analysis, and ensure synthesis readiness of designs.
• Support integration and debug of RTL in simulation and early silicon environments.
• Participate in design reviews and provide technical input on architecture and implementation tradeoffs.
• Work with verification teams to ensure comprehensive functional coverage.
• Assist in timing closure and support backend teams as needed.
• Contribute to continuous improvement of design methodologies, flows, and tools.

Skills

RTL design

Verilog/SystemVerilog

Synchronous digital design

Cross-functional collaboration

Analytical and problem solving

Independent work

AI-assisted workflows

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

VCS

Questa

Verdi

DVE

Job description

Delos Data is seeking a Senior RTL Design Engineer to design, implement, and deliver high-quality RTL for complex digital systems in our Palo Alto office. You will translate architectural specs into scalable microarchitectures using Verilog/SystemVerilog, collaborating with architecture, verification, and physical design teams to meet timing, power, and area goals.

Ideal candidates have 5+ years in RTL design, strong design fundamentals, and hands-on experience with synthesis, linting, and