Senior ML TPU IP Architect - SoC Designer (Equity & Bonus)

Google; Jasper (AL); On-site; USD 163,000 - 236,000; Full time

Job summary

Google seeks a Senior TPU Design Engineer, Silicon, to advance ML IPs for Google Silicon SoCs. You will drive microarchitecture, RTL, and integration for high‑performance ML accelerators, collaborating with cross‑functional teams to push performance and efficiency.

Based in Mountain View or San Diego, you will lead design efforts, mentor juniors, and navigate ASIC flows from RTL to tape-out, focusing on timing, power, and quality.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8 years of experience with RTL design using Verilog/SystemVerilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Responsibilities

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for ML processors and accelerators with data-flow and integration requirements for Subsystem Development.
• Drive RTL development, and debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Skills

RTL design

Verilog/SystemVerilog

IP/SoC leadership

ARM-based SoCs

ASIC methodology

Education

Bachelor's degree in EE/CE/CS

Master's degree (preferred)

Job description

Google seeks a Senior TPU Design Engineer, Silicon, to advance ML IPs for Google Silicon SoCs. You will drive microarchitecture, RTL, and integration for high‑performance ML accelerators, collaborating with cross‑functional teams to push performance and efficiency.

Based in Mountain View or San Diego, you will lead design efforts, mentor juniors, and navigate ASIC flows from RTL to tape-out, focusing on timing, power, and quality.