RTL Design Engineer: AI/ML Accelerator IP & TPU

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Benefits offered by this job

15% bonus target

Equity options

Comprehensive benefits

Job summary

Google Inc. in Sunnyvale, CA is seeking an experienced engineer for an ASIC design role focused on management and control subsystem design. The successful candidate will work on SystemVerilog RTL for ASIC products and collaborate with architecture, validation, and hardware teams.

Applicants should have a Bachelor’s degree in Electrical Engineering or a related field and possess significant experience in ASIC design. The position offers a competitive compensation package including a bonus and equity options.

Qualifications

• Bachelor's degree in a relevant field or equivalent practical experience.
• 8 years of experience in ASIC design.
• Experience interacting with software and hardware teams.

Responsibilities

• Design RTL Intellectual Property focusing on management and control.
• Develop SystemVerilog RTL for ASIC products.
• Collaborate with teams to evaluate features and their impact.

Skills

Experience with scripting languages

Understanding of digital design fundamentals

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree or PhD in related fields

Tools

SystemVerilog

I2C

SPI

UART

Job description

Google Inc. in Sunnyvale, CA is seeking an experienced engineer for an ASIC design role focused on management and control subsystem design. The successful candidate will work on SystemVerilog RTL for ASIC products and collaborate with architecture, validation, and hardware teams.

Applicants should have a Bachelor’s degree in Electrical Engineering or a related field and possess significant experience in ASIC design. The position offers a competitive compensation package including a bonus and equity options.