RTL Design Engineer, TPU and ML

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 198,000; Full time

Job summary

Google is seeking an RTL Design Engineer for the TPU team in Sunnyvale, CA to shape next‑gen AI accelerators. You will design and verify microarchitecture and RTL in SystemVerilog, collaborating with DV, PD, and firmware to deliver high‑quality hardware.

The role focuses on On‑Chip Network and integration of TPU blocks, with opportunities to optimize timing, area, and power while contributing to cross‑functional design flows and post‑silicon support.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing‑critical RTL development.
• Design experience optimizing for performance, power, and area.
• Experience with digital design fundamentals and microarchitecture design.
• Experience working cross‑functionally with DV and PD teams.

Responsibilities

• Define and document complex microarchitecture for the TPU, writing high‑quality, performant, and power‑efficient RTL code primarily in SystemVerilog.
• Partner with cross‑functional teams to drive block‑level and chip‑level integration efforts for the machine learning accelerators.
• Collaborate closely with the verification team to develop robust test plans, debug RTL, and guarantee overall functional correctness.
• Support post‑silicon validation and debugging efforts while contributing to the continuous enhancement of internal design tools, flows, and methodologies.
• Work closely with the physical design team to meet timing, area, power, and manufacturability requirements.

Skills

RTL design

SystemVerilog

ASIC design

Cross‑functional collaboration

Performance/power/area optimization

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's or PhD preferred

Tools

Linting

CDC

RDC

LEC

Job description

corporate_fare Google place Sunnyvale, CA, USA

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

In this role, you will join the team designing and developing the On‑Chip Network of Google's next‑generation Tensor Processing Units (TPUs), the custom‑built accelerators powering our AI and machine‑learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross‑functional teams, including verification, physical design, validation, and firmware, to deliver hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows.

As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions.

US: $138000 - $198000 (USD) + 15% bonus target + equity + benefits

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing‑critical RTL development.
• Design experience optimizing for performance, power, and area.
• Experience with digital design fundamentals and microarchitecture design.
• Experience working cross‑functionally with DV and PD teams.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 4 years of RTL design experience.
• Experience with Linting, CDC, RDC, LEC.
• Experience with scripting languages (i.e. Python or Perl).
• Experience with integration.
• Experience optimizing RTL solutions, RTL design methodologies and automating front‑end engineering flows.

Responsibilities

• Define and document complex microarchitecture for the TPU, writing high‑quality, performant, and power‑efficient RTL code primarily in SystemVerilog.
• Partner with cross‑functional teams to drive block‑level and chip‑level integration efforts for the machine learning accelerators.
• Collaborate closely with the verification team to develop robust test plans, debug RTL, and guarantee overall functional correctness.
• Support post‑silicon validation and debugging efforts while contributing to the continuous enhancement of internal design tools, flows, and methodologies.
• Work closely with the physical design team to meet timing, area, power, and manufacturability requirements.

EEO Statement

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.