Senior ML TPU SoC RTL Design Architect

Google; San Diego (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a senior hardware engineer to drive RTL design and microarchitecture for ML IP within Google Silicon SoCs. You will collaborate across hardware and software teams to deliver high-performance, power-efficient accelerators and cohesive subsystem integration.

The role includes leading RTL development, timing and power estimation, and silicon bring-up on FPGA and final silicon. In-person interviews are expected; preferred locations include Mountain View, CA and San Diego, CA.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Responsibilities

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Skills

RTL design

Verilog/SystemVerilog

Microarchitecture

ARM-based SoCs

IP/SoC leadership

Interconnects

ASIC methodology

Education

Bachelor's degree in EE/CE/CS or related field

Master’s degree (preferred)

Job description

Google is seeking a senior hardware engineer to drive RTL design and microarchitecture for ML IP within Google Silicon SoCs. You will collaborate across hardware and software teams to deliver high-performance, power-efficient accelerators and cohesive subsystem integration.

The role includes leading RTL development, timing and power estimation, and silicon bring-up on FPGA and final silicon. In-person interviews are expected; preferred locations include Mountain View, CA and San Diego, CA.