Senior RTL Design Engineer — Space ASICs for Starlink

Spacex; Redmond (WA); On-site; USD 165,000 - 270,000; Full time

Benefits offered by this job

Medical, vision, dental

401(k) plan

Paid parental leave

3 weeks paid vacation

10+ paid holidays

Company shuttles

Employee stock purchase plan

Long-term incentives

Job summary

SpaceX in Redmond, WA is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink deployment.

You will work with cross‑disciplinary teams to design, verify, and optimize RTL in Verilog/SystemVerilog, delivering timing‑accurate, synthesis‑clean designs for space and ground infrastructures. The role requires 5+ years of RTL implementation experience, a bachelor’s degree in engineering or CS, and strong HDL tool proficiency.

Qualifications

• Bachelors degree required in EE/CE/CS.
• 5+ years of RTL implementation experience.
• Experience with Verilog/SystemVerilog required.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, integrate into top level and deliver fully verified design.
• Work closely with verification team to ensure design is covered and verified.
• Provide timing constraints for IPs and support physical implementation (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

RTL implementation

Verilog/SystemVerilog

Timing closure

Synthesis

HDL Lint tools

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

EDA tools

HDL simulators

HDL Lint tools

Job description

SpaceX in Redmond, WA is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink deployment.

You will work with cross‑disciplinary teams to design, verify, and optimize RTL in Verilog/SystemVerilog, delivering timing‑accurate, synthesis‑clean designs for space and ground infrastructures. The role requires 5+ years of RTL implementation experience, a bachelor’s degree in engineering or CS, and strong HDL tool proficiency.