RTL Design Engineer: FPGA/ASIC for Starlink

InvestedintheMission; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Job summary

SpaceX is developing cutting‑edge FPGA and ASIC designs for Starlink to deliver space and ground infrastructure hardware. The RTL Design Engineer will design ASICs and/or FPGAs, implement IP for complex SoCs, and participate in the full design lifecycle alongside cross‑functional teams.

You will work with systems, firmware, validation, and product engineering to advance Starlink terminals, satellites, and related technologies, using Verilog/SystemVerilog, HDL simulators, and standard design

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
• 1+ years of RTL design experience using SystemVerilog/Verilog or VHDL.
• Master’s in Electrical/Computer Engineering or related field.
• Experience with ASIC/FPGA system integration.
• Proficiency in Python for scripting.
• Experience with DSP or digital communication datapath blocks.
• Experience with HDL simulators (EDA tools).
• Understanding AXI/AHB/APB protocols.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog.
• Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation.
• Engage in high-level architectural design for FPGA and ASICs.
• Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more.

Skills

RTL Design SV/Verilog

Python scripting

DSP datapath

AXI/APB protocols

Education

Master’s in Electrical/Computer Eng

Tools

HDL simulators

Job description

SpaceX is developing cutting‑edge FPGA and ASIC designs for Starlink to deliver space and ground infrastructure hardware. The RTL Design Engineer will design ASICs and/or FPGAs, implement IP for complex SoCs, and participate in the full design lifecycle alongside cross‑functional teams.

You will work with systems, firmware, validation, and product engineering to advance Starlink terminals, satellites, and related technologies, using Verilog/SystemVerilog, HDL simulators, and standard design