Sr. ASIC Design Engineer [Silicon Engineering]

WarmStart Ltd; Irvine, Northern (CA, KY); Hybrid; USD 150,000 - 210,000; Full time

Job summary

SpaceX is seeking a Senior ASIC Design Engineer to contribute to the Silicon Engineering team and develop next-generation ASICs for Starlink hardware. The role focuses on RTL implementation, verification, and timing closure, with collaboration across verification and physical design teams.

The ideal candidate has 5+ years of RTL experience and a strong background in high-speed, low-power ASIC design, earning opportunities tied to cutting-edge space infrastructure projects.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
• Define micro-architecture, implement RTL in Verilog/SystemVerilog, and deliver fully verified designs.
• Collaborate with verification team to ensure design coverage and verification.
• Provide timing constraints for IPs and support physical implementation in synthesis and timing.
• Participate in silicon bring-up and validation.

Skills

RTL implementation

ASIC/SoC integration

AXI/AHB protocols

EDA tools

Problem solving

Education

Bachelor's degree in EE/CE/CS

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX is seeking a motivated and proactive Senior ASIC Design Engineer to join its Silicon Engineering team. This role involves developing next-generation ASICs for deployment in space and ground infrastructures, contributing to the Starlink project, which aims to provide fast and reliable internet globally. The ideal candidate will work with cross-disciplinary teams to enhance the performance and capabilities of the Starlink network.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
• Define micro-architecture, implement RTL in Verilog/System Verilog, and deliver fully verified, synthesis/timing clean designs.
• Collaborate with the verification team to ensure comprehensive design coverage and verification.
• Provide timing constraints for IPs and support the physical implementation team in synthesis and timing closure.
• Participate in silicon bring-up and validation.

Qualifications

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.

Skills

• Problem-solving skills, particularly in clock domain crossings and power optimization.
• Experience in ASIC/SoC system integration and embedded CPU subsystems.
• Familiarity with standard bus protocols (e.g., AXI, AHB).
• Knowledge of high-speed and low-power design techniques.
• Experience with EDA tools such as HDL simulators and HDL Lint tools.
• Team-player with a can-do attitude, capable of working well in a group while contributing individually.
• Eagerness to learn new skills and tackle challenges.