Space-Grade FPGA/ASIC Design Engineer for Starlink

United States Digital Space LLC; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Long‑term incentives (stock)

Discretionary bonuses

Employee Stock Purchase Plan

Medical, vision, dental

401(k) retirement plan

Disability insurance

Life insurance

Paid parental leave

Paid vacation (3 weeks)

10+ paid holidays

Paid sick leave

Job summary

United States Digital Space LLC is seeking an FPGA/ASIC Design Engineer (Silicon Engineering) to design, verify, and optimize next‑generation FPGAs and ASICs for Starlink deployment. You will collaborate with cross‑functional teams across systems, firmware, and software to deliver high‑reliability space hardware.

The role requires a strong background in RTL design, Verilog/SystemVerilog, and FPGA/ASIC integration, with experience in DSP/datapath blocks and modem design.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
• 1+ years of RTL Design experience using SystemVerilog, Verilog or VHDL.
• Master’s degree in Electrical/Computer Engineering or related field preferred.
• ASIC/FPGA system integration experience.
• Proficiency in Python, C/C++, and Bash.
• Experience with DSP, digital communication datapath blocks, or modem design.
• Experience with EDA tools (HDL simulators, Lint tools, FPGA tools) like VCS, Questa, IES, Spyglass, Vivado, Quartus II.
• Experience with AXI/AHB/APB protocols.
• Strong EE fundamentals.
• Experience debugging PCBs with oscilloscopes and spectrum analyzers.
• Team player with cross‑functional collaboration.
• Willingness to learn new skills.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects using Verilog/SystemVerilog.
• Optimize designs for power, performance and area.
• Participate in full ASIC/FPGA design lifecycle from concept to validation.
• Develop tools to analyze data collected on orbit and in the lab.
• Engage in high‑level architectural design for test systems and interoperability.
• Collaborate with software engineers to deliver production software for your designs.

Skills

RTL Design

Python

C/C++

Bash

DSP datapath

Modem design

Cross‑functional teamwork

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

Master’s degree in Electrical/Computer Engineering or related field

Tools

HDL simulators (VCS, Questa, IES)

Spyglass

Xilinx Vivado

Altera Quartus II

Job description

United States Digital Space LLC is seeking an FPGA/ASIC Design Engineer (Silicon Engineering) to design, verify, and optimize next‑generation FPGAs and ASICs for Starlink deployment. You will collaborate with cross‑functional teams across systems, firmware, and software to deliver high‑reliability space hardware.

The role requires a strong background in RTL design, Verilog/SystemVerilog, and FPGA/ASIC integration, with experience in DSP/datapath blocks and modem design.