Senior RTL/ASIC Design Engineer (Silicon)

Latent AI; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Job summary

SpaceX is looking for a motivated Sr. RTL Design Engineer to develop next-generation ASICs for applications in space and ground infrastructures. The ideal candidate will have a Bachelor’s degree in a relevant field and over 5 years of RTL design experience. Responsibilities include evaluating architectural trade-offs and working closely with cross-disciplinary teams to deliver verified designs.

Join an innovative team contributing to the future of broadband internet through the Starlink project.

Qualifications

• 5+ years of experience in RTL implementation.
• Ability to work extended hours or weekends as needed.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
• Define micro-architecture, implement RTL in Verilog/System Verilog, and ensure full verification.

Skills

Problem-solving

ASIC/SoC integration

Embedded CPU subsystems

High-speed design techniques

Scripting skills (Python)

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX is looking for a motivated Sr. RTL Design Engineer to develop next-generation ASICs for applications in space and ground infrastructures. The ideal candidate will have a Bachelor’s degree in a relevant field and over 5 years of RTL design experience. Responsibilities include evaluating architectural trade-offs and working closely with cross-disciplinary teams to deliver verified designs.

Join an innovative team contributing to the future of broadband internet through the Starlink project.