Senior RTL Design Engineer – Next-Gen Space ASICs

InvestedintheMission; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space systems.

You will collaborate with cross-disciplinary teams across systems, firmware, architecture, validation, and ASIC to deliver silicon for space and ground infrastructures worldwide. Responsibilities include RTL implementation in Verilog/SystemVerilog, defining micro-architecture, timing constraints, and silicon bring-up.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in RTL implementation.

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation.

Skills

RTL implementation

Verilog/SystemVerilog

Clock domain crossings

Power optimization

ASIC/SoC integration

Embedded CPU subsystems

AXI/AHB protocols

High speed design

Low power design

Python scripting

HDL simulators

HDL lint tools

Team collaboration

Learning new skills

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

HDL simulators

HDL Lint tools

Job description

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next‑generation ASICs for Starlink and space systems.

You will collaborate with cross-disciplinary teams across systems, firmware, architecture, validation, and ASIC to deliver silicon for space and ground infrastructures worldwide. Responsibilities include RTL implementation in Verilog/SystemVerilog, defining micro-architecture, timing constraints, and silicon bring-up.